FIG. 10 shows a conventional chip packaging structure that includes a metal leadframe 10, which is pressed at two opposite lateral sides or all four sides to form a plurality of strip-like leads 101 arranged in a predetermined manner. Each of the leads 101 is further pressed at a predetermined position to form a downward projection 102, a lower end surface 103 of which serves to electrically contact with external elements. An adhesive tape 20 is attached to a top of the leads 101 of the leadframe 10, and a semiconductor chip 30 is fixedly mounted on the adhesive tape 20. The chip 30 is electrically connected to each of the leads 101 via a metal wire 40, and an insulating sealing material 50 is applied to seal all outer surfaces of the chip 30 and a bottom side of the leadframe 10 to expose only the lower end surfaces 103 of the leads 101 for electrically connecting to external elements, such as a circuit board.
The above-described conventional chip packaging structure is a technique being widely employed in current chip packaging. However, it requires complicate and troublesome pressing and forming process before packaging the leadframe 10 and the chip 30. It is more difficult to accurately control the process and the quality of the leadframe 10 in the above-described chip packaging technique when the chip 30 is kept reduced in volume, and the cost for quality control is inevitably increased under this circumstance. The leadframe 10 also has adverse influences on the miniaturization of the whole chip packaging structure. Moreover, the sealing material 50 used to seal the chip 30 and the leadframe 10 after the metal wires 40 have been soldered to the chip 30 and the leads 101 frequently damages the metal wires 40 or contacts thereof in the process of applying the sealing material 50, resulting in many defects in the completed chip packaging structure, and accordingly costs in subsequent quality test and control.
It is therefore tried by the inventor to develop a chip packaging structure without leadframe to overcome the drawbacks existed in the conventional chip packaging techniques.